From established OEM/ODMs to start-ups, working on diverse product lines within multiple products poses several difficulties. MindTree understands the need to make an informed decision, factoring in technical feasibility, features, costs, ergonomics - and even what customers are likely to pay. Market surveys can help provide insight into customer behavior, but the other details must come from architecture and engineering study. MindTree can assist conducting this study at a fraction of the cost and time required for overall product development.

Our consulting services include:

Product Feasibility Analysis Services

MindTree can provide product feasibility analysis reports for product ideas or concepts before you enter the realization phase. These comprehensive reports cover everything from the different architectures possible, to the volume BOM cost for each of the chosen architectures.

Our product realization feasibility services involve the following steps:

• Requirements study
• Study of the existing product in the market for features, form factor, and cost; discussions and direction setting for further activities, including tear-down analysis
• Exploration of different architecture for features, performance, cost, end-of life of components, manufacturability, RoHS, power consumption, and more
• Presenting the option for discussion
• Reworking architecture to identify workable options
• Estimating costs of prototype and volume manufacturing
• Final Recommendations

High Speed Interface Design Services

As performance requirements escalate, component sizes decrease - and brings along a host of crosstalk and EMI problems. MindTree can help use high-speed interfaces for high performance, while meeting electrical specifications and form factor. Beginning with thorough analysis of the circuit and generating exact, reliable layouts, we help you design high-speed hardware interfaces like DDR2, DDR3, PCI-Express, and RAMBUS.





MindTree’s high-speed interface design flow comprises the following steps:

Architecture/Schematic

This phase defines work done from requirement specification till the schematic. During this phase SI engineers form ideas about the different interfaces and their specifications, such as data rate for DDR SDRAM, bus width, number of loads for address bus, and more.

Modeling and Validation

Modeling and validation involves acquiring and validating models like IBIS, SPICE, and Behavioral for devices, and interconnect models for connectors. If IBIS Models are not available, standard buffer models that meet the drive strength are used in the FPGA.

Simulation Constraints

During this design phase SI engineers come up with the Noise and Timing Budget.

Pre-Layout SI

Pre-layout SI analysis can be used to select technology for I/Os, clock distributions, chip package types, component types, board stack up, pin assignments, net topologies, and termination strategies. Batch SI simulations on different corner cases will progressively formulate a set of optimized guidelines for physical designs at a later stage. The objective is to ensure that signal integrity of the physical layout (which follows the placement/routing constraints for Noise and Timing Budget) will not exceed the maximum allowable noise levels.

Placement and Routing

After the pre-layout phase, SI design is passed to the layout engineer for constraint-driven place and route.

Post-Layout SI

Post-layout SI verifies the correctness of SI design guidelines and constraints. It checks SI violations in the current design, such as reflection noise, ringing, crosstalk, and ground bounce. It may also uncover SI problems that are overlooked in the pre-route stage, providing more accurate simulation results. Once Post-layout SI results meet Noise and Timing Budget requirements, the design is sent for FAB and assembly.

Measurement and Analysis

This phase involves signal quality measurements on assembled boards. The relationship between different signals is also measured to ensure that results are similar to those observed during simulations. In case of mismatched results, further analysis is performed to isolate the cause of the problem, and a solution is found.