MindTree has the right mixture of circuit and Layout design engineers who understand and practice all types of engineering techniques in the area of Analog/Mixed signal design, standard cell design and other type of development like PDK & Characterization. Our Expert teams, especially in the Analog Layout areas can deliver high-quality solution in areas of memory layout, IO Layout, Full chip design, etc. Our proven expertise and multiple successful customer engagements make us a perfect partner to join with.
Our Offerings

Accomplishments
We have expertise in the following areas
Standard Cell/Custom based Digital Experience
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Layout Design Techniques
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IO Memory Designs
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- Combinational Cells
- Muxes, Latches, Flip-flops, Buffers, Adders
- Design techniques for standard cells
- Grid based standard cell techniques
- Single/double height cells
- Area/Delay/power optimizing techniques
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- Matching techniques for differential circuits
- Latch Up techniques for CMOS Circuits
- ESD techniques for input/output circuitry
- Antenna techniques for metal routings
- Deep sub micron techniques
- Electro migration techniques for current caring
- IR drop reduction techniques for power management blocks
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- IO Circuit Design
- Memory Design of ROM & RAM
- Interfacing IO's with Analog and Memory
- ESD and Latch up Designs
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Why MindTree
- We have an experienced team of Analog Designers with experience range varying from 0 to 20 years.
- We have the exposure to multiple foundries such as TSMC, UMC, ST, Polar and TI.
Sample Case Studies
- Development of Battery charger chip with thermal regulation and Programmable charge current for a leading PC peripherals development company
- Design migration from TSMC to UMC for a leading US based memory vendor
- Library development work for multiple leading Fabless Design Houses in 32nm, 40nm, 65nm and 90 nm nodes
- Mixed Signal verification and layout work for PWM processor for a leading US based Analog semiconductor company